This invention relates to an improved serial-to-parallel converter which uses shift registers and latch circuits and in particular to a serial-to-parallel converter composed of CMOS transistor circuits.
There is shown in FIG. 6(a) a conventional type of serial-to-parallel converter wherein n memory cells (or bit stages) SR1 to SRn are connected in series and successively shift the input serial data Da in synchronism with a shift clock .phi.. A latch pulse L.sub.P is generated when the data Da inputted at the first memory cell SR1 finally reach the last memory cell SRn. The output data from the memory cells are latched to the n latch circuits L.sub.1 to L.sub.n to generate output signals O.sub.1 to O.sub.n, thus completing the serial-to-parallel conversion. New serial data are inputted thereafter from the first memory cells SR1 and the same process is repeated. FIG. 6(b) shows the operation timing signals of the circuit of FIG. 6(a).
With a circuit structure as shown in FIG. 6(a), however, a shift register may reverse its polarity by the input of shift clock .phi. even before the input serial data are transmitted, depending upon the initial state of the shift register. Such reversals in memory cells result in a waste of power. When the circuit is made of CMOS transistors, in particular, the primary advantage of using CMOS circuits may not be fully utilized.
It is therefore an object of this invention to eliminate such problems of a conventional circuit of this type and to reduce the number of reversals, thereby providing a serial-to-parallel converter with a reduced rate of power consumption.